Time-of-day apparatus receiving standard time code broadcast

ABSTRACT

A standard broadcast receiving time-of-day apparatus capable of using a crystal oscillator of low accuracy and saving the power consumption. This includes a receiver for receiving the standard broadcast, a time unit using a quartz oscillating circuit, and a time controller for calibrating an internal time-of-day signal which the time unit counts by using the standard time-of-day signal superimposed on the standard broadcast, and the time controller requires and stores a deviation between the internal time-of-day signal and the standard time-of-day signal and calibrates the internal time-of-day signal by using the stored deviation when failing to receive the standard broadcast. A clock pulse extracted from the carrier wave of the standard broadcast may be counted for a predetermined period and the frequency deviation of an internal clock may be calibrated by checking the count number of the internal clock counted for the above period. Or, the internal clock may be calibrated by using the carrier wave of the standard broadcast as a reference clock of the PLL circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a time-of-day apparatus for receiving astandard time code broadcast and performing time-of-day calibration.

2. Description of the Related Art

Japan Standard Time is consistently transmitted by means of LF (lowfrequency) broadcasts from two stations in Japan which are directlymanaged by the independent corporation, Communications ResearchLaboratory. Hereafter, the LF broadcast for transmitting the JapanStandard Time described above is referred to as “Standard Broadcast.”Currently, there are two standard broadcasts respectively of carrierfrequencies 40 kHz and 60 kHz, and these LF waves of the differentcarrier frequencies are transmitted respectively from the abovestations.

The carrier wave of the standard broadcast is subjected to the pulseamplitude modulation, according to the time-of-day data pulse string ofthe Japan Standard Time converted into the digital signal of apredetermined format. The time-of-day data pulse string is constitutedof one frame of 60 bits/minute and the one frame includes thetime-of-day data such as year, month, day and hour, minute, second. Thebit rate of the time-of-day data pulse string is defined as 1bit/second.

The time-of-day apparatus for receiving the standard broadcast,calibrating time-of-day, and displaying the calibrated time-of-day is inwide use as a so-called radio-wave clock (refer to Japanese Patent KokaiNo. 2002-131456 (Patent Document 1)). The outline of the radio-waveclock will be described below.

At first, upon receipt of the standard broadcast, a radio receiver ofthe radio-wave clock amplifies the received signal to a predeterminedlevel and then, extracts the signal components near the carrierfrequency by using a band-pas filter of a predetermined bandwidth. Then,it detects the extracted signal components and demodulates them into thetime-of-day data pulse string of the Japan Standard Time superimposed onthe standard broadcast. A digital processor of the radio-wave clockreproduces the digital signals indicating the time-of-day data from thedemodulated time-of-day data pulse string and supplies the same to atime unit of the radio-wave clock. Based on the reproduced digitalsignals, the time unit calibrates the internal time-of-day which its ownquartz oscillating circuit is counting, and displays the time-of-day ateach instant. Owing to the above structure, the radio-wave clock candisplay the extremely accurate time-of-day in synchronization with theJapan Standard Time.

The receiving condition of the standard broadcast in the radio-waveclock varies greatly depending on its setting place and environmentalconditions. For example, if the radio-wave clock is placed in a housewith steel-reinforced concrete walls or on a basement floor of abuilding, the receiving condition would significantly be deterioratedbecause of the attenuation of the arriving wave. Also, if there exist anumber of sources of radio wave noises around the radio-wave clock, thereceiving condition of the radio-wave clock would be deteriorated by theinfluence of such noises. As mentioned above, since the radio-wave clockcontains the quartz oscillating circuit for time-of-day counting, evenwhen the radio-wave clock falls into a state incapable of receiving thestandard broadcast correctly, the display time-of-day of the radio-waveclock will not turn to be incorrect immediately.

When the reception fail state continues for a long time, however, thereis a possibility of causing an error in the display time-of-daydepending on the accuracy of a crystal oscillator used for a quartzoscillating circuit included in the radio-wave clock. Accordingly, inorder to decrease the error of the display time-of-day, it is necessaryto use a crystal oscillator of high accuracy and naturally thisincreases the manufacturing cost disadvantageously.

The radio-wave clock generally operates the radio receiverintermittently in order to save the power consumption. Accordingly, whenthe time intervals of the intermittent operation are expanded, the powerconsumption can be saved, but when the receiving condition isdeteriorated, the reception fail state continues for a long time and anerror in the displayed time-of-day is easy to happen. While, when thetime intervals are shortened, an error in the display time-of-day can bedecreased even in the case where the receiving condition isdeteriorated, but the power consumption is increased disadvantageously.

The invention has been made in order to solve the above problems, and anobject to be solved by the invention is to provide a standard broadcastreceiving time-of-day apparatus that can reduce the power consumptioneven with a crystal oscillator of low accuracy.

SUMMARY OF THE INVENTION

A standard broadcast receiving time-of-day apparatus according to theinvention is to receive the standard broadcast, extract the timeinformation and the frequency information included in the above wave,and correct the deviation of the measurement time inside the system andthe deviation of the oscillation frequency of the quartz oscillatingcircuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a first embodiment of the standardbroadcast receiving time-of-day apparatus according to the invention.

FIG. 2 is a time chart showing the operation in the embodiment of FIG.1.

FIG. 3 is a time chart showing the operation in the conventionalradio-wave clock.

FIG. 4 is a view showing an example of variation in the time-of-daydeviation according to a change of ambient temperature in a day.

FIG. 5 is a block diagram showing a fourth embodiment of the standardbroadcast receiving time-of-day apparatus according to the invention.

FIG. 6 is a block diagram showing a fifth embodiment of the standardbroadcast receiving time-of-day apparatus according to the invention.

FIG. 7 is a block diagram showing a sixth embodiment of the standardbroadcast receiving time-of-day apparatus according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

A first embodiment of the standard broadcast receiving time-of-dayapparatus according to the invention will be described based on theblock diagram of FIG. 1.

As shown in FIG. 1, the system according to this embodiment chieflycomprises a radio receiver unit 10, a controller 20, and a clock unit30.

The radio receiver unit 10 is mainly formed by the circuits including areceiving antenna, a high frequency amplifier, a band-pass filter, and adetector, and it plays a role of receiving, detecting, and demodulatingthe standard broadcast. Although it is not shown in FIG. 1, it isneedless to say that the radio receiver unit 10 includes variousauxiliary circuits including an AGC circuit and an AFC circuit which arenaturally to be equipped in a general low frequency receiver.

The controller 20 is constituted mainly of a microcomputer, memoriessuch as ROM and RAM, and various circuits of the peripheral units (noneof which are illustrated). In the memories, a main program and variouskinds of subprograms (none of which are illustrated) for defining theoperations of the respective units are stored. The microcomputercontrols the whole operations of the system by running these programs insynchronization with a predetermined clock.

The clock unit 30 is constituted mainly of a quartz oscillating circuitfor time-of-day count, a time-of-day display panel, and various kinds ofcircuits such as a display panel driving circuit (none of which areillustrated). On the time-of-day display panel, the time-of-day at eachinstant and the other calendar data are displayed. It is needless to saythat the display time-of-day on the clock unit 30 is properly controlledby the controller 20.

The block diagram of the system shown in FIG. 1 is only an exemplaryembodiment of the invention, but the classification of each component isnot restricted to this structure. For example, the controller 20 and theclock unit 30 may be integrated into one circuit, and additionally, theradio receiver unit 10 and the above may be integrated into one circuit.

The internal time-of-day generating unit in Claims corresponds to theclock unit 30 and the time controller corresponds to the controller 20.Similarly, the time-of-day deviation storing device and theself-calibrating component in Claims correspond to the processingoperation means run in the microcomputer within the controller 20.

The operation of the first embodiment according to the invention will bedescribed with reference to the time chart shown in FIG. 2. In the timechart shown in this figure, the radio receiver unit 10 is assumed tooperate intermittently at the time intervals of T. In the followingdescription, Japan Standard Time received from the standard broadcastwill be referred to as the standard time-of-day signal and the timewhich the quartz oscillating circuit within the clock unit 30 countswill be referred to as the internal time-of-day signal.

At first, the controller 20 performs the initial time calibration toadjust the internal time-of-day signal to the Japan Standard Time, byusing the standard time-of-day signal received through the firstreceiving operation of the standard broadcast after starting theoperation of the system. The above initial time calibration may beperformed by the first receiving operation of the standard broadcastjust after power-on, or it may be performed by receiving the standardbroadcast just after a user's input of a predetermined resetinstruction. Alternatively, it may be performed by the combination ofthe above conditions.

After the initial time calibration, the quartz oscillating circuit ofthe clock unit 30 continuously counts the internal time-of-day signal. Acrystal oscillator included in the above circuit generally has afrequency deviation at its manufacturing time. When this frequencydeviation is positive, the quartz oscillating circuit by using thecrystal oscillator arrives at the count number, which the quartzoscillating circuit having no deviation can count for a predeterminedperiod, earlier than the above predetermined period of time. This isdefined as a negative time-of-day deviation, and in the contrary case,namely when the crystal oscillator has a negative frequency deviation,this is defined as a positive time-of-day deviation.

In the system of FIG. 1, assuming that the crystal oscillator used forthe quartz oscillating circuit has the positive frequency deviation, thenegative time-of-day deviation occurs in the internal time-of-daysignal, as mentioned above. This time-of-day deviation is graduallyincreased with the elapse of time, resulting in a time lag between theinternal time-of-day signal and the standard time-of-day signal.

In the time chart of FIG. 2, when the time T has passed since the firstreceiving operation of the standard broadcast and the second receivingoperation of the standard broadcast is correctly performed, thecontroller 20 performs the time calibration for calibrating the internaltime-of-day signal by using the second received standard time-of-daysignal.

In the calibration by the received time-of-day, the controller 20requires the standard time-of-day signal received at second and thetime-of-day deviation Δt between the internal time-of-day signal and theabove signal. By advancing the internal time-of-day signal by Δt, theinternal time-of-day signal is synchronized with the standardtime-of-day signal. Owing to this, as shown in FIG. 2, the negativetime-of-day deviation gradually increased with the elapse of time isonce cleared into zero.

This embodiment is characterized in that the time-of-day deviation At isonce stored in the memory within the controller 20 and that, what iscalled, the self-time-of-day calibration of calibrating the internaltime-of-day signal by using the Δt is performed when the receivingoperation of the standard broadcast in the third time and later is notperformed normally.

Namely, in the conventional radio-wave clock, when the third receivingoperation and the subsequent operations are not performed normally dueto the deterioration of the receiving state, it becomes naturallyimpossible to calibrate the internal time-of-day signal, as shown in thetime chart of FIG. 3. Thus, as shown in the same diagram, thetime-of-day deviation once cleared by the second receiving operation ofthe standard time-of-day signal is continuously increased in thenegative direction thereafter, and a time lag between the internaltime-of-day signal and the standard time-of-day signal is much moreincreased according to this increase of the time-of-day deviation.

On the contrary, this embodiment, even in the case of failing in thethird receiving operation of the standard broadcast and failing toobtain the standard time-of-day signal, as shown in FIG. 2, theself-time-of-day calibration for calibrating the internal time-of-daysignal by using the time-of-day deviation At stored in the memory withinthe controller 20 is performed at this receiving timing. Thus, thetime-of-day deviation occurring between the standard time-of-day signaland the internal time-of-day signal is cleared again into zero. Further,even in the case of failing in the fourth and later receiving operationof the standard broadcast, since the self-time-of-day calibration isperformed in the same procedure as the above, synchronization betweenthe internal time-of-day signal and the standard time-of-day signal isalways maintained.

In the case of succeeding in receiving the standard broadcast at thestandard broadcast receiving timing of the fourth and later whereby thestandard time-of-day signal from the standard broadcast is obtained, theinternal time-of-day signal at the timing is calibrated by the receivedtime-of-day signal. When the correct standard time-of-day signal isobtained at the next standard broadcast receiving timing, a newtime-of-day deviation At is obtained according to the deviation from theabove standard time-of-day signal and the new value is stored in thememory of the controller 20.

As mentioned above, according to the embodiment, time accuracy can beimproved by performing the self-time-of-day calibration of the internaltime-of-day signal. According to this, it is possible to use aninexpensive crystal oscillator having a large frequency deviation forthe quartz oscillating circuit within the system.

Since the time intervals of the intermittent receiving operation of thestandard broadcast can be expanded according to a decrease of thetime-of-day deviation through the self-time-of-day calibration, it ispossible to maintain the power consumption in the radio receiver unit10.

In the above embodiment, although the time-of-day deviation between thestandard time-of-day signal and the internal time-of-day signal isacquired by the continuous two receiving operations of the standardbroadcast, the time-of-day deviation may be acquired from, for example,a plurality of receiving operations of the standard broadcast by usingthe static method. Alternatively, with a plurality of time-of-daydeviations stored, the optimum time-of-day deviation may be acquired byusing these values according to the static method.

Next, the second embodiment of the standard broadcast receivingtime-of-day apparatus according to the invention will be described.

Since the structure of the hardware of the system in the embodiment isthe same as that of the first embodiment, the block diagram shown inFIG. 1 is to be referred to in the following description. Thisembodiment is to be used together in the case of performing theself-time-of-day calibration of the internal time-of-day signal whenfailing to receive the standard broadcast in the first embodiment.

Generally, the ambient temperature at which the standard broadcastreceiving time-of-day apparatus is set varies periodically in a day.While, the frequency deviation of the crystal oscillator has atemperature characteristic varying depending on its ambient temperature.Accordingly, the frequency deviation of the crystal oscillator includedin the quartz oscillating circuit of the standard broadcast receivingtime-of-day apparatus varies periodically in a day. As described in thefirst embodiment, a variation of the frequency deviation of the crystaloscillator appears as a time lag between the internal time-of-day signalthe quartz oscillating circuit counts and the standard time-of-daysignal received from the standard broadcast, namely the time-of-daydeviation.

Here, assume that there occurs the time-of-day deviation as shown inFIG. 4 at each standard time in a day (24 hours), according to theambient temperature change in a day in the system of FIG. 1. The valuesof the time-of-day deviation can be obtained through calibration byusing the standard time-of-day signal received at each standard time.For example, the time-of-day deviation between the standard time-of-daysignal received at the timing of two o'clock in the standard time andthe internal time-of-day signal at that time becomes Δt2 and thetime-of-day deviation between the standard time-of-day signal receivedat the timing of four o'clock in the standard time and the internaltime-of-day signal at that time becomes Δt4.

In the embodiment, each time-of-day deviation is acquired at eachstandard time in a day (24 hours) and each value is stored in the memorywithin the controller 20. Although a time-of-day deviation is acquiredin every two hours in FIG. 4, the embodiment is not restricted to this,but the time intervals of requiring and storing the time-of-daydeviation may be set at any time.

The controller 20 stores the time-of-day deviation at a predeterminedtime in a day into the memory. When all the time-of-day deviations ateach predetermined time are stored there, the controller 20 is toperform the self-time-of-day calibration of the internal time-of-day byusing the time-of-day deviation stored in the memory. For example, whenfailing to receive the standard broadcast at the timing of 4 o'clock inthe standard time and therefore failing to calibrate the internaltime-of-day signal, the controller 20 performs the self-time-of-daycalibration of the internal time-of-day signal by adding the time-of-daydeviation Δt4 stored in the memory to the time-of-day deviationcorrection value Δt in the first embodiment.

Therefore, according to the embodiment, it is possible to furtherimprove the time accuracy and to use a cheap crystal oscillator having alarge frequency deviation for the quartz oscillating circuit. Further,it is possible to restrain the power consumption in the radio receiverunit 10 according to the expansion of the intervals of the intermittentreceiving operations of the standard broadcast.

In the above description, although the structure of performing theself-time-of-day calibration of the internal time-of-day signal, withthe time-of-day deviations over 24 hours once stored, has beendescribed, the embodiment is not restricted to this. For example, thetime-of-day deviations over 24 hours may be stored repeatedly and thestatistical processing of the average of the movements may be performedon the stored data, thereby requiring the more suitable time-of-daydeviation.

Next, the third embodiment of the standard broadcast receivingtime-of-day apparatus according to the invention will be described.

Since the hardware structure of the system in this embodiment is thesame as that of the first embodiment, the block diagram shown in FIG. 1is to be used in the following description. Further, although theembodiment is to be used together in the case of performing theself-time-of-day calibration of the internal time-of-day signal whenfailing to receive the standard broadcast in the first embodiment, itmay be performed in combination with the second embodiment.

Generally, as a change of the ambient temperature has a predeterminedperiodicity in a day, a change of the ambient temperature has aperiodicity in a year. Since the data about the date is included in thestandard time-of-day signal of the standard broadcast, the standardbroadcast receiving time-of-day apparatus can recognize the date at apoint of receiving the standard broadcast. Therefore, when thetime-of-day deviations accompanying a change of the ambient temperaturein a year are stored in the memory of the controller 20, it is notimpossible to calibrate the time-of-day deviations accompanying a changeof the ambient temperature in a year according to the same method as thesecond embodiment.

However, storing all the time-of-day deviations accompanying a change ofthe ambient temperature in a year into the memory is not economical fromthe viewpoint of the capacity of the memory, and in consideration ofvarious environmental conditions under which the system is set, theabove method is not practical.

A change of the ambient temperature in a day generally has a correlationto a change of the ambient temperature in a year. For example, under theair-conditioned and temperature-controlled environment, a temperaturechange in a day is small and at the same time, a temperature change in ayear is also small. Therefore, it is quite possible to predict thetime-of-day deviations accompanying a change of the ambient temperaturein a year, based on the measured data of the time-of-day deviationsaccording to a change of the ambient temperature in a day.

In this embodiment, first, the data about the year periodicity of thetime-of-day deviations accompanying the standard change of the ambienttemperature is stored in the memory of the controller 20 in a form ofROM table. In consideration of the periodicity of the time-of-daydeviation data accompanying a change of the ambient temperature in aday, which has been collected in the above-mentioned second embodiment,the correction value of the time-of-day deviation is determined in everymonth or every season in a year.

For example, the controller 20 prepares the time-of-day deviation dataaccording to a change of the standard ambient temperature in a day (24hours) and requires the proportionality constant for calibration of thetime-of-day deviation by comparison with the measured data of thetime-of-day deviations in a day obtained in the above second embodiment.The measured data for several days may be prepared in order to decreasean error caused by scattering of the data and then, the proportionalityconstant may be acquired by using the statistical method.

The controller 20 calculates the standard predicted correction value ofa year from the data about the year periodicity of the time-of-daydeviation stored in the ROM table, multiplies the calculated correctionvalue by the proportionality constant obtained in the above, andrequires the time-of-day deviation correction value in every month orevery season in a year.

The controller 20 is to perform the self-time-of-day calibration byadding the above-obtained time-of-day deviation correction value of ayear to the internal time-of-day signal when performing theself-time-of-day calibration of the internal time-of-day signal.

According to the embodiment, the self-time-of-day calibration is enabledby predicting a change of the ambient temperatures in a year and it ispossible to further improve the time accuracy. Therefore, it is possibleto use a cheap crystal oscillator having a large frequency deviation fora quartz oscillating circuit and to restrain the power consumption inthe radio receiver unit 10 according to the expansion of the timeintervals of the intermitting receiving operations of the standardbroadcast.

The fourth embodiment of the standard broadcast receiving time-of-dayapparatus according to the invention will be described.

The structure of the system in the embodiment is shown in the blockdiagram of FIG. 5. The block diagram is to show only the portionsconcerned with the embodiment of the invention, and the description ofthe portions not directly concerned with the embodiment of theinvention, for example, the description of the display of the time andits driving circuit, is omitted.

The structure of the embodiment will be described with reference to FIG.5.

An antenna 101 in FIG. 5 is a low frequency receiving antenna such as aloop antenna and a ferrite antenna. The standard broadcast of lowfrequency transmitted from the standard broadcast station is modulatedby the antenna 101 and received by the system as a feeble signal.

The high frequency amplifier 102 is a high frequency amplifier foramplifying a feeble received signal from the antenna 101 to apredetermined level, and the signal amplified by the above amplifier issupplied to the band-pass filter 103. The band-pass filter 103 is aband-pass filter of high selectivity (high Q) using, for example, acrystal oscillator and to attenuate the frequency component other thanthe main lobe bandwidth of the standard broadcast included in thereceived wave.

The received signal detector 104 is a circuit for amplifying thereceived signal extracted by the band-pass filter 103 to a predeterminedlevel and detecting this. In order to realize the waveform of theenvelope of the received signal faithfully, the received signal detector104 is provided with an AGC function for properly controlling theamplification of the amplifier included in the same circuit according toits detected output.

The detected output signal from the received signal detector 104 issupplied to a low-pass filter 105 and the component of the carrierfrequency of the standard broadcast included in the detected outputsignal is removed by the same filter, thereby reproducing the waveformof the envelope of the received signal.

The output of the low-pass filter 105 is further compared with apredetermined threshold voltage Vref1 according to a voltage comparator106, and it is converted into a pulse string of digital signal havingtwo values including high amplitude level and low amplitude level. Thispulse string turns into the standard time-of-day signal indicating oneframe of the standard time.

The standard time-of-day signal that is the output of the voltagecomparator 106 is supplied to the controller 20 of the standardbroadcast receiving time-of-day apparatus, hence to be used for theprocessing such as time calibration by reception and time display, butthe description about such signal and processing is omitted because theyhave no concern directly with the structure of the embodiment.

While, the received signal extracted by the band-pass filter 103 is alsosupplied to a carrier signal detector 107. Though the above detector hasthe same structure as the above received signal detector 104, since itis to extract the component of the carrier frequency not envelope thewaveform of the received signal, the set value of the AGC function inthe above detector is different from that of the received signaldetector 104.

The component of the carrier frequency included in the received signalis detected and extracted by the carrier signal detector 107 andsupplied to the voltage comparator 108. The voltage comparator 108compares the detected output with a predetermined threshold voltageVref2 and converts this into a clock pulse of digital signal. The clockpulse is in synchronization with the received standard carrier wave andhas the same cycle as the carrier frequency. In the followingdescription, this clock pulse is to be referred as a carrier clocksignal.

A carrier counter 109 is a so-called preset down-counter and to countdown the initial set value of the counter set by the controller 20described later by using the above carrier clock signal. It is needlessto say that a control such as starting the count operation is performedby the controller 20.

A clock counter 110 is an up-counter of counting up a source clocksignal supplied from the quartz oscillating circuit 121 included in aclock generator 120 described later. Though a count start of the clockcounter 110 is instructed from the controller 20, a count stop is to beperformed by an overflow signal occurring when the count initial setvalue becomes zero in the carrier counter 109. The count value of theclock counter 110 is to be notified to the controller 20 at apredetermined timing.

The controller 20 is mainly formed by a microcomputer, memories such asROM and RAM, and various circuits of these peripheral units (none ofwhich are illustrated). A main program and various kinds of subprograms(none of which are illustrated) for defining the operations of therespective units of the system are stored in the memories. Themicrocomputer controls the operations of the whole system by runningthese programs in synchronization with a predetermined clock.

The clock generator 120 is mainly formed by a quartz oscillating circuit121 and a divider 122. The quartz oscillating circuit 121 is anoscillating circuit using a crystal oscillator, which provides thesource clock signal that is the output therefrom, to the divider 122 andthe above clock counter 110. The divider 122 is a dividing circuit fordividing the source clock signal according to a predetermined dividingratio and the dividing ratio is to be set by the controller 20. Thedivided clock is supplied to the respective units within the systemincluding the controller 20 as an internal clock signal. The clockgenerator 120 (quartz oscillating circuit 121) is always in anoscillating state.

The internal time-of-day signal is counted by using this internal clocksignal in the system. This embodiment is to calibrate the accuracy ofthe internal clock signal by using the carrier frequency of the standardbroadcast having the definite accuracy, thereby improving the timeaccuracy in this system.

The operation of the embodiment will be described by taking the concretenumerical examples. It is needless to say that the embodiment of theinvention is not restricted to these numerical examples.

First, the controller 20 sets the value of “5,120,000” as the initialset value for counting down in the carrier counter 109 in the initialsetting. This numeric value means the assumption that the carrierfrequency is 40 kHz and that the measurement hour of the counter is 128seconds. Namely, the number of the count pulses of the carrier clocksignal (40 kHz) within the measurement hour (128 seconds)40,000×128=5,120,000becomes the initial set value for counting down of the carrier counter109.

Assume that the numeric value of “32, 768” is set in the divider 122within the clock generator 120 as the dividing ratio by the controller20.

Upon completion of the above initial setting, the controller 20 notifiesthe carrier counter 109 and the clock counter 110 of a reset/startinstruction. According to this, the carrier counter 109 starts thecounting down of the initial set value and at the same time, the clockcounter 110 starts counting up the source clock signal from the quartzoscillating circuit 121.

In the carrier counter 109, when the count value arrives at zero as aresult of the continuous counting down of the initial set value, anover-flow signal notifying this is supplied to the clock counter 110 andthe controller 20 respectively. The clock counter 110 stops thecounting-up operation upon receipt of the signal. While, the controller20 takes in the count value obtained by the clock counter 110 havingcounted up the source clock signal at a predetermined timing.

Assuming that the count value is “4,194,176”, the controller 20calculates the count value per one second4,194,176/128=32,767by dividing this by the time 128 seconds required for the countingoperation.

The calculated value becomes the dividing ratio for the source clocksignal in order to obtain the internal clock signal of the same cycle asthat of the carrier clock signal.

As mentioned above, since the dividing ratio initially set in thedivider 122 is “32,768”, the frequency deviation in this case becomes(32,768-32,767)/32,768=30.5 ppm.

The controller 20 sets the above calculated value “32,767” in thedivider 122 within the clock generator 120 as a new dividing ratio.

In this embodiment, it is possible to always calibrate the frequencydeviation of the internal clock signal by constantly repeating theabove-mentioned operations. Thus, the same effect as the first to thethird embodiments as mentioned above can be obtained.

It is needless to say that the calibration of the internal clock signalof the standard broadcast receiving time-of-day apparatus according tothis embodiment may be performed by combination with the calibration ofthe time-of-day deviation shown in the first to the third embodiments asmentioned above.

This time, the fifth embodiment of the standard broadcast receivingtime-of-day apparatus according to the invention will be described.

The structure of the apparatus according to the embodiment is shown inthe block diagram of FIG. 6. This diagram is to show only the portionsconcerned with the embodiment of the invention and the description ofthe portions not directly concerned with the embodiment of theinvention, for example, the description of the time display and thedriving circuit, is omitted.

First, the structure of the embodiment will be described referring tothe same diagram.

The antenna 201 in FIG. 6 is a low frequency receiving antenna such as aloop antenna and a ferrite antenna. The standard broadcast of lowfrequency transmitted from the standard broadcast station is modulatedby the antenna 201 and received by the system as a feeble signal.

The high frequency amplifier 202 is a high frequency amplifier foramplifying a feeble received signal from the antenna 201 to apredetermined level, and the signal amplified by the amplifier issupplied to an analog multiplier 203. The analog multiplier 203 is amixer using a modulator including an average modulator and a ringmodulator, for multiplying the output signal from the high frequencyamplifier 202 by the output signal from the voltage controlled-quartzoscillating circuit 221 which will be described later.

The received signal detector 204 is a circuit for amplifying the outputsignal from the analog multiplier 203 to a predetermined level anddetecting this. In order to realize the waveform of the envelope of theoutput signal from the analog multiplier 203 faithfully, the receivedsignal detector 204 is provided with an AGC function for properlycontrolling the amplification of the amplifier included in the samecircuit according to its detected output.

The detected output signal from the received signal detector 204 issupplied to a low-pass filter 205 and the component of the carrierfrequency of the standard broadcast included in the detected outputsignal is removed by the same filter, thereby reproducing the waveformof the envelope of the detected output signal.

The output of the low-pass filter 205 is further compared with apredetermined threshold voltage Vref1 according to a voltage comparator206, and it is converted into a pulse string of digital signal havingtwo values of high amplitude and low amplitude. This pulse string turnsinto the standard time-of-day signal indicating one frame of thestandard time-of-day signal. The standard time-of-day signal that is theoutput of the voltage comparator 206 is supplied to the controller 20hence to be used for the processing such as time calibration throughreception and received time-of-day display, but the description aboutthis processing is omitted because they do not directly relate to thestructure of the embodiment.

While, the output signal from the analog multiplier 203 is also suppliedto the carrier detection amplifier 207 and the output signal from theamplifier is applied to one input of a phase comparator 208. The phasecomparator 208 is a circuit for supplying a signal according to thefrequencies and the phase deviation of the two input signals by using,for example, an exclusive OR circuit. The output signal from the voltagecontrolled-quartz oscillating circuit 221 described later is supplied tothe other input of the phase comparator 208.

The output signal of the phase comparator 208 is supplied to thelow-pass filter (loop filter) 209, where the high frequency component isremoved from the output signal, and then passing through asample-and-hold circuit 210, it is supplied to the voltagecontrolled-quartz oscillating circuit 221. The gate control of thesample-and-hold circuit 210 is to be performed by the controller 20described later.

The voltage controlled-quartz oscillating circuit 221 is a voltagecontrolled-oscillator in combination with a variable capacity elementsuch as varactor diode and a quartz oscillating circuit, and itsoscillation frequency is adjusted according to the direct voltageapplied through the sample-and-hold circuit 210. Assume that theoscillation frequency of the voltage controlled-quartz oscillatingcircuit 221 is set at the vicinity of the carrier frequency (40 kHz or60 kHz) of the standard broadcast.

It is needless to say that the above-mentioned phase comparator 208,loop filter 209, and voltage controlled-quartz oscillating circuit 221forms a so called PLL (Phase Locked Loop) circuit.

The controller 20 is mainly formed by a microcomputer, memories such asROM and RAM, and various circuits of these peripheral units (none ofwhich are illustrated). The main program and various kinds ofsubprograms (none of which are illustrated) for describing theoperations of the respective units are stored in the memories. Themicrocomputer controls the operations of the whole system by runningthese programs in synchronization with a predetermined clock.

The output signal from the voltage controlled-quartz oscillating circuit221 corresponds to the internal clock signal of the system and thisinternal clock signal is used to count the internal time-of-day signalin this system. The embodiment is to calibrate the internal clock signalby synchronizing the internal clock frequency with the carrierfrequency, by using the carrier frequency of the standard broadcastwhose accuracy is defined, as a reference clock of the PLL circuit.

This time, the operation of the embodiment will be concretely described.

The received signal passing through the high frequency amplifier 202 issubjected to the multiply modulation processing by the output signalfrom the voltage controlled-quartz oscillating circuit 221, in theanalog multiplier 203, hence to enhance the selectivity of the carrierfrequency. The above modulation processing is nothing but the multiplyprocessing of the above two signals. Therefore, the waveform of theenvelope of the output signal from the analog multiplier 203 becomes thewaveform of the pulse frequency of the standard time-of-day signal whichhas been superimposed on the carrier of the standard broadcast byamplitude modulation.

As mentioned in the fourth embodiment, the output signal from the analogmultiplier 203 is applied to the received signal detector 204 to besubjected to the predetermined processing, and then reproduced as thestandard time-of-day signal.

While, passing through the carrier detection amplifier 207, the outputsignal of the analog multiplier 203 enters the PLL circuit including thephase comparator 208, the loop filter 209, and the voltage-controlledquartz oscillating circuit 221 as a reference clock. The other inputinto the phase comparator 208 forming the PLL circuit is the internalclock signal that is the output signal from the voltagecontrolled-quartz oscillating circuit 221.

The phase comparator 208 creates a phase comparative signal between theoutput signal of the analog multiplier 203, namely the carrier clocksignal, and the internal clock signal and supplies this to the loopfilter 209. The loop filter 209 removes the high frequency componentincluded in this phase comparative signal and extracts the directcurrent component from the same signal. Therefore, the direct currentvoltage in proportion to the degree of the deviation in the phasefrequency between the carrier clock signal and the internal clock signalis generated in the output of the loop filter 209.

The direct current voltage enters the sample-and-hold circuit 210. Asmentioned above, the gate of the sample-and-hold circuit 210 iscontrolled by a control signal from the controller 20. Before thesynchronization is established between the internal clock signal and thecarrier clock signal, the controller 20 performs a control of making thesample-and-hold circuit 210 through. According to this, the directcurrent output voltage from the loop filter 209 is applied to thecontrol input of the voltage controlled-quartz oscillating circuit 221and the voltage controlled-quartz oscillating circuit 221 oscillates theinternal clock signal of the frequency according to the above voltage.

When the reception of the standard broadcast has got stable and thepull-in of the PLL circuit (lock of the PLL circuit) has been completed,the controller 20 controls the sample-and-hold circuit 210 to be locked,and according to this, the control voltage of the voltagecontrolled-quartz oscillating circuit 221 is fixed, hence to fix theoscillation frequency. Thereafter, even when the reception of thestandard broadcast is interrupted, the voltage controlled-quartzoscillating circuit 221 continues the oscillation of the internal clocksignal of the stable frequency.

As mentioned above, according to the embodiment, since the PLL circuitcan be used to calibrate the accuracy of the internal clock signal bysynchronizing the above signal with the carrier clock signal, the sameeffect as the first to the third embodiments can be obtained.

It is needless to say that the calibration of the internal clock signalof the standard broadcast receiving time-of-day apparatus according tothe embodiment can be performed by combination with each calibration ofthe time-of-day deviation shown in the first to the third embodiments.

Since the selectivity of the carrier frequency of the standard broadcastis enhanced by using the analog multiplier, the band-pass filter of highselectivity (high Q) is not necessary in the former step of thedetector, thereby decreasing the number of crystal oscillators requiredin the system.

The sixth embodiment of the standard broadcast receiving time-of-dayapparatus according to the invention will be described.

The structure of the system according to the embodiment is shown in theblock diagram of FIG. 7. This block diagram is to show only the portionsconcerned with the embodiment of the invention, but the description ofthe portions not directly concerned with the embodiment of theinvention, for example, the description of the time-of-day display andthe driving circuit is omitted.

The structure of the embodiment will be described with reference to FIG.7. This embodiment is based on the fifth embodiment, and to calibratethe internal clock frequency by using the carrier frequency of thestandard broadcast as a reference clock of the PLL circuit. Therefore,only the portions added to the structure of the fifth embodiment aredescribed hereafter.

In FIG. 7, a connection switch 310 is a signal switching circuit byusing an analog signal switching element such as analog switch and amercury relay, and the switching instruction is performed by a controlsignal form the controller 20. The sample-and-hold circuit 210 in thefifth embodiment is not used in this embodiment.

An analog/digital converter 313 is a circuit for converting a controlvoltage applied to a voltage controlled-quartz oscillating circuit 321into a digital signal and the digital signal output from the aboveconverter is read by the controller 20 at a predetermined timing. Adigital/analog converter 314 is a circuit for converting the digitalsignal supplied from the controller 20 into an analog signal at apredetermined timing.

The concrete operation of this embodiment will be described. Thefollowing description will be made about only the portions differentfrom the above-mentioned fifth embodiment.

At first, at the initial time when the system starts receiving thestandard radio wave, the connection switch 310 switches the switchingconnection to the side of A as shown in FIG. 7, according to the controlsignal from the controller 20. Thus, the output of the loop filter 309is connected to the control voltage input of the voltage-controlledoscillating circuit 321 and the same operation of the PLL circuit as thefifth embodiment is performed.

During the operation of the PLL circuit, the analog/digital converter313 operates, sequentially converts the value of the control voltageapplied to the voltage-controlled oscillating circuit 321 into a digitalsignal, and notifies the controller 20 of this value. The controller 20can always monitor the change of the control voltage during theoperation of the PLL circuit.

The controller 20 stores the state of the operation of thevoltage-controlled oscillating circuit 321 according to the change ofthe control voltage, and judges the information about the stableoperation such as jitter in the PLL circuit. Judging that the operationof the PLL circuit has got stable, a control of the voltage-controlledoscillating circuit 321 is directly switched from the PLL control to thedirect control by the controller 20.

Here, the direct control by the controller 20 means the control methodfor controlling the oscillating frequency by the controller 20 whichdirectly supplies a proper control voltage to the voltage-controlledoscillating circuit 321.

Namely, the controller 20 supplies a predetermined digital signal to thedigital/analog converter 314 to generate a proper control voltage. Next,a switching control signal is supplied to the connection switch 310 andthe switching connection is switched to the side of B shown in FIG. 7.According to this, a control voltage input of the voltage-controlledoscillating circuit 321 is connected to the output of the digital/analogconverter 314 and the oscillating frequency is controlled by the controlvoltage supplied from the same converter.

The controller 20 operates the analog/digital converter 313 again afterperforming the switching operation and reads the control voltage of thevoltage-controlled oscillating circuit 321 to judge whether the value iscorrect or not.

According to the embodiment, since the oscillating frequency of thevoltage-controlled oscillating circuit 321 can be controlled directlyfrom the controller 20, it is possible to adjust the oscillatingfrequency in consideration of the correction of the time-of-daydeviation according to a change of the ambient temperature, for example,mentioned in the second and the third embodiments. In this case, sincethe internal clock frequency itself, not the time-of-day deviation, canbe corrected, it is possible to supply the stable clock signal to theoutside of the system.

According to the embodiment, the controller 20 can monitor the controlvoltage of the voltage-controlled oscillating circuit 321 at any time.Therefore, the controller 20 can smoothly find a state of causing arelease of the phase lock of the PLL circuit due to the deterioration ofthe receiving state of the standard broadcast and a lock difficultstate, and therefore, a control by the PLL circuit can be properlyswitched to a control by the controller 20, hence to obtain the stableinternal clock signal.

As mentioned above, according to the embodiment, since the internalclock signal can be synchronized with the carrier clock signal by usingthe output from the PLL circuit and the controller 20, hence tocalibrate the accuracy, it is possible to obtain the same effect as theabove-mentioned first to third embodiments.

It is needless to say that calibration of the internal clock of thestandard broadcast receiving time-of-day apparatus can be performed incombination with the calibration of the time-of-day deviation shown inthe first to the third embodiments.

Further, since the selectivity of the carrier frequency of the standardbroadcast can be enhanced by using the analog multiplex, a band-passfilter of high selectivity (high Q) is. not necessary in the prior stepof the detector and therefore, it is possible to decrease the number ofcrystal oscillators required in the system.

This application is based on Japanese Patent Application No. 2003-137784which is herein incorporated by reference.

1. A standard broadcast receiving time-of-day apparatus including a radio receiver for receiving a standard broadcast, an internal time-of-day generating unit for generating an internal time-of-day signal by using a quartz oscillating circuit, and a time controller for calibrating the internal time-of-day signal based on a standard time-of-day signal superimposed on the standard broadcast, wherein the time controller comprises a time-of-day deviation storing device for detecting and storing a time-of-day deviation between the internal time-of-day signal and the standard time-of-day signal and a self-calibrating component for calibrating the internal time-of-day signal by using the time-of-day deviation stored in the time-of-day deviation storing device when failing to receive the standard broadcast.
 2. The standard broadcast receiving time-of-day apparatus according to claim 1, wherein the time controller further comprises a second time-of-day deviation storing device for storing a time-of-day deviation caused by a change of ambient temperature at every standard time for every day, and when calibrating the internal time-of-day signal, the self-calibrating component reads out the time-of-day deviation caused by the change of the ambient temperature at the calibration time, so to calibrate the internal time-of-day signal based on the above time-of-day deviation.
 3. The standard broadcast receiving time-of-day apparatus according to claim 2, wherein the time controller further comprises a third time-of-day deviation storing device for storing tendency data of the time-of-day deviation caused by the change of the ambient temperature for every year, and when calibrating the internal time-of-day signal, the self-calibrating component reads out the time-of-day deviation caused by the change of the ambient temperature at the calibration time, so to calibrate the internal time-of-day signal based on the above time-of-day deviation.
 4. The standard broadcast receiving time-of-day apparatus according to claim 3, wherein the time controller corrects the data stored in the third time-of-day deviation storing device according to the tendency of the time-of-day deviation data stored in the second time-of-day deviation storing device.
 5. A standard broadcast receiving time-of-day apparatus for calibrating time by receiving a standard broadcast, comprising: a carrier wave clock generator for extracting a component of carrier wave from the standard broadcast and converting the component into a clock signal; a first counter for counting down a predetermined count value of initial setting by using the clock signal; an internal clock generator for dividing a clock signal from a quartz oscillating circuit according to the predetermined dividing ratio, so to generate an internal clock signal; a second counter for starting count of the clock signal from the quartz oscillating circuit according to a count starting instruction and stopping the count upon completion of counting down by the first counter; and a controller for setting the count value of the initial setting in the first counter, supplying the count starting instruction to the second counter, and setting the count value at a time of stopping the count of the second counter as the predetermined dividing ratio in the internal clock generator.
 6. The standard broadcast receiving time-of-day apparatus for calibrating time by receiving a standard broadcast, comprising: a multiplier for multiplying a received signal of the standard broadcast by the internal clock signal; a control voltage generator for generating a control voltage based on a phase deviation between an output signal from the multiplier and the internal clock signal; and a clock signal generator, including a quartz oscillating circuit capable of adjusting an oscillating frequency according to the control voltage, for generating the internal clock signal.
 7. The standard broadcast receiving time-of-day apparatus according to claim 6, further comprising: an analog/digital converter for converting the control voltage into a digital signal; a digital/analog converter for converting a predetermined digital signal into the control voltage signal; a connection switch for connecting the clock signal generator to the control voltage generator or the digital/analog converter in a switchable way, according to a signal of connection switching instruction; and a controller for reading a digital signal from the analog/digital converter, writing a predetermined digital signal into the digital/analog converter, and supplying the signal of connection switching instruction to the connection switch, at a predetermined timing. 